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| GSM Receiver Circuit PMB 2402 Preliminary Data Bipolar IC Features q Heterodyne receiver with demodulator q Down mixing from 900 MHz receiver band to the base q q q q q q q q q q q q q band Demodulation and generation of I/Q-baseband components Low mixer noise 10 dB (SSB) Input high intercept point + 2 dB Integrated 0 and 90 phase shifter 82 dB AGC-range On-chip second LO-oscillator with external tuning circuit Two differential operational amplifiers Low power consumption due to highly flexible powerdown capability Wide input frequency range up to 1 GHz Wide IF-range from 35 MHz to 100 MHz Wide output frequency range up to 13.5 MHz P-DSO-28-4 shrink package Temperature range - 25 C to 85 C P-DSO-28-4 Applications q Digital mobile cellular systems as GSM, DAMPS, JDC q Various demodulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK q Space and power saving optimizations of existing discrete demodulator circuits Type PMB 2402S PMB 2402S Version V 2.1 V 2.1 Ordering Code Q67000-A6072 Q67006-A6072 Package P-DSO-28-4 (Shrink, SMD)) P-DSO-28-4 (Shrink, SMD, Tape + Reel) Functional Description The PMB 2402 is a single-chip single-conversion heterodyn PM-receiver with phase shifting circuitry for the I/Q-phase baseband demodulation on chip. It also includes the second local oscillator, a gain controlled second IF-amplifier, two differential operational amplifiers for baseband filtering purposes and power down circuitry. The PMB 2402 is designed for digital mobile telephones according to the GSM-standard and other digital systems. Semiconductor Group 1 01.94 PMB 2402 Pin Configuration (top view) Semiconductor Group 2 PMB 2402 Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol SOI SOQ INQ OUTQ OUTQ INQ SOQ LO2E LO2B GND IFI IFI GC LO2O MO MO Function Non-inverting in-phase signal output Non-inverting quadratur signal output Inverting op. amp. signal output (Q) Non-inverting op. amp. signal output (Q) Inverting op. amp. signal output (Q) Non-inverting op. amp. signal intput (Q) Inverting quadratur signal output External capacitors for oscillator VCO-tuning circuit Ground Inverting IF input Non-inverting IF input Gain control input VCO-signal output Inverted output of first mixer Non-inverted output of first mixer Supply voltage Non-inverted signal input of first mixer Inverted signal input of first mixer Power-down input 1 Non-inverting input for first local oscillator Inverting input for first local oscillator Power-down input 2 Inverting in-phase signal output Non-inverting op. amp. signal input (I) Inverting op. amp. signal output (I) Non-inverting op. amp. signal output (I) Inverting op. amp. signal input (I) VS SI SI PD1 LO1 LO1 PD2 SOI INI OUTI OUTI INI Semiconductor Group 3 PMB 2402 Block Diagram Semiconductor Group 4 PMB 2402 Circuit Description The input signal SI/SI and the amplified first local oscillator signal LO1/LO1 are mixed down to an intermediate frequency (IF). The open collector output of the mixer generates a differential current at pins MO/MO which is filtered by an external resonant circuit. The resulting voltage drives an external SAW-filter. The second local oscillator signal LO2 is generated in an on chip VCO and is fed to two dividers, which generate orthogonal signals at a quarter of VCO-frequency. The internal LO-signal is fed to an additionally divider, whose output signal LO2O is fed to the RF-signal of PLL-synthesizer. The filtered IF-signal reenters the chip at the IFI/IFI input, where it is amplified and demodulated to the final baseband output frequency with each of the orthogonal signals. The resulting in-phase and quadrature signals pass through differential output drivers and appear at SOI/SOI and SOQ/SOQ outputs, respectively. The amplification of the IF-signal before the second mixer stage is performed by a gain-controlled amplifier, the gain being determined by the voltage at the gain control input GC. Two differential operational amplifiers with the input signals INI/INI (INQ/INQ) and the output signals OUTI/OUTI (OUTQ/OUTQ) can be used as active filters. Differential signals and symmetrical circuitry are used throughout, except at the signal output. Bias drivers generate internal temperature- and supply voltage-compensated reference voltages required by various circuit blocks. Switching the power down inputs PD1 and PD2 from high to low (see table) sets the circuit from its normal operating mode into a mode with reduced supply current. PD1 L L H H PD2 L H L H RF-Part OFF OFF ON ON IF-Part OFF ON OFF ON VCO/Divders ON ON ON ON Semiconductor Group 5 PMB 2402 Internal Input / Output Circuits Semiconductor Group 6 PMB 2402 Electrical Characteristics Absolute Maximum Ratings The maximum ratings may noy be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. TA = - 25 C to 85 C Parameter Supply voltage Input/output voltage (any except open collector) Open collector output voltage (MO/MO) Differential input voltage (any differential input) Junction temperature Storage temperature Thermal resistence (junction to ambient) Symbol min. Limit Values max. 7 V V V V V V C C K/W K/W PDSO-28 P-DSO-28-S - 0.5 - 0.5 - 0.5 - 0.5 - 0.5 -3 Unit Remarks VS VIO VOC VI Tj Tstg Rth JA VS + 0.5 7.5 VS 7 V VS 7 V VS 5 V VS 5 V VS + 2.5 7.5 3 125 - 55 125 55 Semiconductor Group 7 PMB 2402 Operational Range Within the operational range the IC operates as described in the circuit description. The AC/DCcharacteristics limits are not guaranteed. VS = 4.5 V to 5.5 V; TA = - 25 C to 85 C; refer to test circuit 1. Parameter SI/SI input level SI/SI input frequency LO1/LO1 input level LO1/LO1 input frequency Intermediate frequency IFI/IFI input level IFI/IFI input frequency LO2 input level LO2 input frequency VCO frequency range LO2O output level LO2O output frequency SOI/SOI, SOQ/SOQ output Bandwidth GC input voltage L-PD1/PD2 voltage H-PD1/PD2 voltage Symbol Limit Values min. max. - 11 1000 - 11 35 35 - 20 140 120 120 15 0 0 0 4 3 1100 100 - 24 100 0 400 250 180 50 13.5 2 1 dBm MHz dBm MHz MHz dBm MHz dBm MHz MHz mVpp MHz MHz V V V - 3 dB roll off with ext. capacitors VCO external Unit Remarks PSI fSI PLO1 fLO1 fIF PIFI fIFI PLO2 fLO2 fVCO PLO2O fLO2O BSO VGC VPDL VPDH VS Note: Power levels are referred to resistance of 50 Semiconductor Group 8 PMB 2402 AC/DC Characteristics AC/DC-characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. VS = 4.75 to 5.25 V; TA = 25 C; Parameter Supply current Symbol Limit Values min. typ. 5.5 15.5 15 24.5 max. 6.8 19 18.5 30 mA mA mA mA PD1 = L PD1 = L PD1 = H PD1 = H PD2 = L PD2 = H PD2 = L PD2 = L 3.1 12 11.5 20 Unit Test Condition Test Circuit 1 IS First Mixer Signal Input SI/SI Input resistance Input inductance Max. input level Input intercept Point Blocking level Input interference level at f = fint Input frequency Noise figure RSI LSI PSI PIPI PB Pint fSI NSI NSI 17 3.5 - 13 0 - 16 - 38 25 5 - 11 2 - 14 33 6.5 3 - 12 nH dBm dBm dBm dBm In series to RSI 1 dB compr. at MO/MO 2a 2a 1 1 1 3 1 DSB-noise, fC = 900 MHz SSB-noise, fC = 900 MHz including optimum noise matching 1 GMO = 14 dB 3 dB attenuation of wanted Signal at MO - 98 dBm interference at f = (fint +/- fLO1) X2 at MO 960 7.5 9.5 8 10 9.5 11.5 MHz dB dB Output of First Mixer MO/MO (open collector) Output resistance RMO RMO 11.2 7 0.7 3.5 16 10 1 5 13 20.8 13 1.3 6.5 14 100 k k pF mA dB MHz fMO = 45 MHz fMO = 71 MHz parallel to RMO 2c 2c 2c 1 1 1 Output capacitance CMO Total output current IMO + MO Power gain from Signal input Intermediate frequency GMO fIF 35 Semiconductor Group 9 PMB 2402 AC/DC-Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit Input of First Mixer Local Oscillator LO1/LO1 Input resistance Input capacitance Input level Input frequency RLO1 CLO1 PLO1 VLO1 fLO1 490 0.7 - 11 178 700 1 910 1.3 3 890 pF dBm mVpp fLO1 = 900 MHz parallel to RLO1 see diagram 1 2a 2a 1 1 1 1100 MHz Isolation of First Mixer From SI SI to MO to LO1 ASI - MO ASI - LO1 30 60 dB dB dB dB dB dB fSI = 945 MHz; fLO1 = 900 MHz fSI = 945 MHz; fLO1 = 900 MHz fSI = 945 MHz; fLO1 = 900 MHz fSI = 945 MHz; fLO1 = 900 MHz fSI = 945 MHz; fLO1 = 900 MHz fSI = 945 MHz; fLO1 = 900 MHz 1 1 1 1 1 1 LO1 to MO LO1 to SI MO to Si MO to LO1 ALO1 - MO 50 ALO1 - SI AMO - SI 60 50 AMO - LO1 65 IF Input IFI/IFI Input resistance Input capacitance Max. input level Input intercept point Input frequency Noise figure RIFI CIFI PIFI VIFI PIPI fSI NSI 63 0.35 90 0.5 - 17 89 117 0.65 pF dBm mVpp parallel to RIFI 2a 2a 1 1 1 VGC = 2 V, 1 dB compr. at SO; see diagram 4 see diagram 5 35 10 11 100 14 MHz dB SSB-noise 1 1 Input for Second Local Oscillator LO2 (VCO external) Input resistance RLO2 1.9 1.3 2.4 1.8 3.1 2.3 k k fLO2 = 180 MHz fLO2 = 360 MHz 2b 2b Semiconductor Group 10 PMB 2402 AC/DC-Characteristics (cont'd) Parameter Input capacitance Input level Input frequency Symbol Limit Values min. typ. 1 max. 1.3 0 630 400 pF dBm mVpp MHz into 50 0.7 - 20 63 140 Unit Test Condition Test Circuit 2b 1.1 1.1 1.1 CLO2 PLO2 VLO2 fLO2 Voltage Controlled Oscillator VCO (LO2) VCO-frequency VCO Output LO2O Output resistance Output level Output frequency fVCO 120 250 MHz with ext. capacitors 1.2 RLO2O VLO2O fLO2O 0.9 0.7 150 120 15 1.2 1 160 140 1.5 1.3 k pF mVpp mVpp IF 75 MHz IF 75 MHz 1 1 1 Output capacitance CLO2O 50 MHz Signal Outputs SOI/SOI, SOQ/SOQ Output resistance SO frequency roll off DC output level Diff. output offset voltage Voltage gain from IF to I/Q-output RSO fSO VSO VSO/SO GSO 175 0.7 250 1 13.5 325 1.3 pF MHz see diagram 6 1 between I/I or Q/Q 1 1 Output capacitance CSO 2.0 2.5 28 V mV dB dB 57 - 25 61 - 21 65 - 17 VGC = 0 V VGC = 2 V see diagram 2 + 3 Gain Control Input GC GC-input voltage GC-input current Gain control factor VGC - IGC 0 40 2 1 V A dB/V 0 V VGC 2 V 1 1 1 FGC FGC = dGSO/dVGC see diagram 3 Semiconductor Group 11 PMB 2402 AC/DC-Characteristics (cont'd) Parameter Symbol Limit Values min. Power-Down Inputs PD1, PD2 L-PD input voltage L-PD input current typ. max. Unit Test Condition Test Circuit VPDL IPD1L IPD2L 0 1 0.1 0.2 V A A V A 4 VPD1, 2L VS 0 VPD1, 2L 1 V 1 1 1 1 H-PD input voltage VPDH H-PD input current 4 VS 10 IPDH Differential Operational Amplifier (open loop) Slew rate Gain Bandwith Prod. Voltage gain Phase margin Gain margin Common mode Rejection Ratio Offset voltage Output voltage SR GBW AVo R AR 4.6 12 55 60 14 58 1 0.8 V/s MHz dB degr. dB dB mV 1 1 1 1 1 1 1 1 CMRR VOFF VOUT VS -1 V Semiconductor Group 12 PMB 2402 Test Circuit 1 Semiconductor Group 13 PMB 2402 Test Circuit 1.1 Test Circuit 1.2 Semiconductor Group 14 PMB 2402 Test Circuit 2a Test Circuit 2b Test Circuit 2c Semiconductor Group 15 PMB 2402 The S-parameters are tested at the indicated frequency and the equivalent parallel or series circuit is calculated on this base. Test Point LO1-input impedance SI-input impedance IFI-input impedance LO2-input impedance MO-output impedance Test Circuit Test Frequency / MHz 2a 2a 2a 2b 2c 900 900 45 ... 90 180, 360 45, 71 Pin x 21 18 11 9 15 Pin y 22 19 12 - 16 Semiconductor Group 16 PMB 2402 Test Circuit 3 f W = wanted input signal from received channel fint = unwanted interfering signal within band : fint = fLO - fIF / 2 fLO = local oscillator signal fIFW = wanted IF signal from received channel = fLO - fW fIFi t = unwanted IF / 2 signal from interfering channel: fIFint = fLO - fint fIF2in = unwanted harmonic signal of fIF2in : fIF2in = 2 x fIFint Semiconductor Group 17 PMB 2402 Application Circuit Semiconductor Group 18 PMB 2402 Diagram 1 First Mixer Gain versus LO-Level PLO1 PSI = - 40 dBm, fMO = 45 MHz Diagram 2 Gain Control Characteristic Output Level PSO versus input Level PIFI Diagram 3 Gain Control Characteristic Voltage Gain GSO versus GC-Voltage VGC Diagram 4 Gain Control Characteristic Max. Input Level PIFI versus GC-Voltage VGC: (1 dB Compresion at SO) Semiconductor Group 19 PMB 2402 Diagram 5 Gain-Control Characteristic Input Intercept Point PIPI versus GC-Voltage VGC Diagram 6 Frequency Transfer Characteristic of Outputs SOI / SOQ Semiconductor Group 20 PMB 2402 Package Outlines Plastic-Package, P-DSO-28-4 (Shrink) (SMD) (Dual-Small-Outlines) Sorts of Packing Package outlines for tubes, trays ect. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Dimensions in mm Semiconductor Group 21 |
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